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PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 1 / 25 PE12016G/24g features: ? functional and pincompatible with obsolete ti cf32007nw/nt / thct12016 / thct 12024 / ls2000 ? 5 v and 3.3 v operation ? 0.6u cmos process ? direction discriminator ? pulse width measurement ? frequency measurement ? cascadable (PE12016G only) ? ttl compatible ? 8 bit parallel tristateable bus ? simple read & write procedure ? high speed 20 mhz clock operation ? PE12016G only: 1:1 replacement for ls2000an ? pe12024g only: 24-bit resolution, separate ua0 counter reset ? weee & rohs compliant according directive 2002/95/ec (green package material) PE12016G pdip28-600 mil pe12024g pdip24-300 mil description : the PE12016G/12024g incremental encoder interface can independently determine the direction or displacement of a mechanical device or axis based on two input signals from transducers in quadrature. alternatively, it can measure a pulse width using a known clock rate, or a frequency, by counting input pulses over a known time interval. it includes one 16-bit or 24- bit counter which may also be used separately (PE12016G only). the PE12016G may be cascaded to provide accuracy greater than 16- bits. both devices are designed for use in many microprocessor-based systems. 28 15 14 1 cs vcc rd up d0 down d1 we d2 reset d3 a0 gnd clk d4 ua2 d5 ua1 d6 m0 d7 m1 borrow m2 carry ready gnd kli-klo 24 13 12 1 cs vcc rd ua0 d0 a1 d1 we d2 reset d3 a0 gnd clk d4 ua2 d5 ua1 d6 m0 d7 m1 gnd m2 www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 2 / 25 PE12016G/24g availability: the PE12016G/24g is available as replacement ic or netlist ip core, fully compatible with the obsolete ti cf32007nw/nt functionality. the replacement ic is packaged within the popular pdip28-600 mil (PE12016G) and the pdip24- 300 mil package (pe12024g). the ip core can be targeted to any desired fpga/cpld or asic technology and is delivered within the according netlist format. the database has been proven in a co-emulation together with the reference part by stimulating both devices with the same inputs and observing the identical results on the outputs. ressource usage ip core: gate count for asic technologies is 1700 gates. for cplds 128 macrocells are needed, resulting in a xilinx xc95144 cpld differences: the PE12016G/24g has some minor enhancements. ua1 and ua2 are synchronized with the clock, eliminating the need to place a discrete act74 type flipflop in front of these signals. due to this feature a latency of one clock cycle is introduced, resulting worst case in a +/-1 counter difference. the output driver capability is slightly decreased. pullups are on the following pins: /a1, /up, /down and /kli-klo. ua0 has a pulldown. the value is approximately 75 kohm. for further details refer to the application notes at the end o f this datasheet. applications: the PE12016G/12024g enables mechanical devices to be interlaced with micro-processors. it may be used in many diverse applications, including robotics, printers/plotters, tracker ball s (or mouse), lathes and machine tools, automobiles, conveyor belts and transport mechanisms. architecture : the four main elements of the PE12016G are shown in fig 2: 1. the measurement and mode control logic generates up or down count pulses, internal signals (i1 and i2) from the quadrature signals ua1 and ua2, the clock input and from mode controls (m0, m1, m2). 2. the control logic provides common microprocessor interface signals. 3. the output multiplexer allows the processor to select data from either the upper (ms-byte) or the lower (ls-byte) 4. the 3-state buffers place this data on the bus the pe12024g-architecture, shown in figure: 3 , is very similar to that of the PE12016G, except for the up/down counter which has 24-bits and can be independently reset by ua0. the cascading feature has also been removed. www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 3 / 25 PE12016G/24g fig. 1: pe 12016g block diagram fig. 2: pe12024g block diagram measurement logic 8-bit up/down- counter 8-bit up/down counter control logic 16 - bit latch 3-state output buffer multiplexer m0 m1 m2 up down ua1 ua2 clk reset ce rd a0 carry borrow kliklo we ready d0......d7 lsb msb measurement logic 24-bit up/down- counter control logic 24-bit latch 3-state output buffer multiplexer m0 m1 m2 ua0 ua1 ua2 clk reset ce rd a1/a0 we d0......d7 lsb msb www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 4 / 25 PE12016G/24g operation: the eight modes of operation of the PE12016G/12024g are summarized in table 1 . mode m2 m1 m0 mode description 0 0 0 0 counter 16-bit (PE12016G only) up/down counter (inhibits di rection discriminator) direction discriminator 1 0 0 1 single count pulse synchronous with ua1 rising in f orward direction and ua1 falling in backward direction. 2 0 1 0 single count pulse synchronous with ua2 rising in f orward direction and ua2 falling in backward direction. 3 0 1 1 double count pulse synchronous with ua1 rising and falling. 4 1 0 0 double count pulse synchronous with ua2 rising and falling. 5 1 0 1 quadruple count pulse synchronous with all edges. 6 1 1 0 pulse width measurement ua1 is the gate signal ua2 is high for up counting and low for down counti ng. count is synchronous with rising clock. 7 1 1 1 frequency measurement ua1 is frequency signal to be measured ua2 is the gate signal of known time interval. count is synchronous with rising edge of ua1. www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 5 / 25 PE12016G/24g table 1: PE12016G/12024g operation modes detailed information about the different modes: mode 0: 16-bit up/down counter mode in this mode the PE12016G may be used as a fast 16-bit up/down counter with cascade capability. this is operated using the /up and /down inputs. the states of the counter outputs are transferred to a 16-bit latch. the contents of this 16-bit latc h are multiplexed on a 8-bit parallel data bus (d0?d7) and enabled using /rd and /cs. /a0 is the control input for the byte multiplexer. a high level at this input transfers the least significant byte to the data outputs; and a low level transfers the most significant byte. the up/down counters are loaded in individual 8- bit bytes by the /wr and /cs signals, with the byte selected by the /a0 input. the counter may be cleared using the /reset signals (which clears both counter and control logic), or individually, using ua0 signal (pe12024g) only. cascading to n-bits is possible using inputs /up and /down, outputs /borrow, /carry and the input-outputs /kli-klo (PE12016G only). note: the pe12024g cannot be used in mode 0 since /up and /down inputs are not available. to read or load the 24-bit (pe12024g only) in all modes, /cs, /rd or /wr, /a0 and /a1 are used to perform the read or write operation. the operation should always start with the lsb (/a0=/a1=high), followed by the lsb+1 (/a0=low, /a1=high) and then the msb (/a0=high, /a1=low). /a0 /a1 byte remarks on d0-d7 h l h h lsb lsb+1 PE12016G only h l l l msb all x pe12024g extensions table 2: pe12024g address select www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 6 / 25 PE12016G/24g mode 1-5 : direction discriminator modes the quadrature signals ua1 and ua2 identify forward or backward directions. if ua1 leads ua2, the forward direction is indicated and the counter will count up; if ua1 lags ua2, the reverse direction is indicated and the counter will count down. fig. 3: direction discriminator modes both ua1 and ua2 are stored on the clock falling edge in the first of a pair of consecutive d-type flip-flops, and are transferred to the next on the clock rising edge. by comparing the states of the four flip-flops and checking the mode inputs, the up or down count pulses are generated; see figures 4 and 5 . fig. 4: direction discriminator up clock www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 7 / 25 PE12016G/24g transducer of resolution speed shaft f _ _ _ = fig. 5: direction discriminator down clock modes 1 to 5 define which edge of the quadrature signals will be counted in accordance with table 1 . the clock frequency should be at least four times greater than the frequencies of the quadrature signals: this will eliminate problems resulting fro m timing jitter in the transducer signals and will allow the quadruple counting mode to be used. the frequency of the quadrature signals, ua1 and ua2 may be calculated from the relationship: mode 6: pulse width measurement mode in this mode, ua1 acts as a gate, and is the pulse width to be measured. synchronised with the clock edge after a low to high transition in ua1, counting begins at the input clock frequency. similarly, synchronised with the clock edge after a high to low transition of ua1, counting is disabled. the value in the counter is loaded in the output register, /kli-klo (PE12016G only) is pulled low and then the counter clears. see figure 7 . if ua2 is held high, the counter will count up, and if ua2 is held low, the counter will count down. each counter can be preloaded in two or three bytes (pe12024g only) by activating /cs, and /we, and selecting the individual bytes with /a0, and/or /a1 after ua1 has fallen and before the next preload takes place. the kli-klo signal (PE12016G only) may be used as an interrupt to indicate to the processor when the output register has been loaded. in the pulse width mode, the output register will not be loaded via /cs and /rd, but by the falling edge of ua1. www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 8 / 25 PE12016G/24g in pulse width mode, the minimum time that can be m easured is: tmin = 2 (to) (accuracy is +/- to) fig. 6: pulse width measurement mode 7: frequency measurement mode in mode 7, ua1 is the signal of unknown frequency to be measured; ua2 is a gate signal of known width. a low to high transition of ua2 enables counting at the frequency of ua1. when the gate (ua2) goes low, counting is disabled. the value of the counter is loaded into the output register, /kli-klo is pulled low (PE12016G only), and the counter is then cleared. see figure 8 . fig. 7: frequency measurement www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 9 / 25 PE12016G/24g reset operation: a total reset is initiated by pulling the /reset pi n low. this will clear the counters to zero, reset th e d flip-flops at the inputs of the quadrature signal s (ua1 and ua2), clear the latches that inhibit the load register pulse, and load zero into the register. to avoid a spurious count error (+/- 1) after a reset, the ua1 and ua2 inputs should be held to the values indicated in table 3 during and just after the reset pulse. mode ua1 ua2 0 x x 1-5 h h 6-7 l l table 3: ua1 and ua2 levels during reset operations note: if a /reset=low appears during a read or write cycl e of the PE12016G, the /ready output will stay low as long /reset is active. cascading devices (PE12016G only) the /kli-klo pins of all cascaded PE12016G?s should be tied together, so that all of the devices load their output registers at the same time. when the ?master? generates a pulse for the other PE12016Gs, /kli-klo on the ?master? works as an output, and /kli-klo on the ?slaves? work as inputs. the /carry output of one device should be tied to the /up input of the next device in the cascade. similarly, /borrow should be connected to /down. write operation a number may be preloaded into the counter by pulling /cs and /we low while using /a0 /a1* (/a1* pe12024g only) to direct the value on the data bus to the selected byte of the counter. this will cause /ready (PE12016G only) to go low on the next falling clock edge, and remain low until /cs or /we goes high. see figure 10 . www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 10 / 25 PE12016G/24g read operation when in modes 0 to 5 the contents of the counter can be read at any time by pulling /cs and /rd low. the most significant byte may be selected by setting /a0 low, and the least significant byte may be read by setting /a0 high (PE12016G only, for pe12024g ? see table 2 ). this will cause a ?load output register? pulse to be generated and /kli-klon will go low during the next low clock pulse. /ready (PE12016G only) will also go low as the clock goes low, and will stay low until /cs and/or /rd go high. the load output register pulse stores the current value of the counter in a 16-bit or 24-bit latch register: / a0 and /a1 (pe12024g only) direct the selected byte through a multiplexer to the outputs : /cs and /rd also enable the 3-stat outputs ? see figure 9 . the output register will be loaded immediately if /kli-klo (PE12016G only) is pulled low externally; this signal normally comes from a cascaded device. for modes 6 & 7 see the earlier description of these modes. configuration special consideration should be paid to the automatic configuration features of the PE12016G/12024g. the purpose of these features is to allow for the different order of byt e reads (high then low or low then high) of different processors when doing a word read across a byte wide bus and also to automatically configure when devices are cascaded. byte order configuration after a system reset has occurred, the first read operation will store the value of /a0 /a1 into a latch within the device. from that time until the next system reset the load output register pulse will only be generated during a read operation if /a0 /a1 is at this stored value. this means that the internal load output register pulse is correctly generated for word operations regardless of the byte order of the particular processor. special care should be taken when reading individual bytes to ensure that these operations are always done in a consistent order. cascaded configuration (PE12016G only) after a system reset the first device and channel to receive a read operation (/rd and /cs = low) configures itself into ?master? mode and outputs a pulse on /kli-klo. in cascaded operation the /kli-klo pins of the cascaded channels are connected together and the input pulse on /kli- klo of the cascaded channels configures these to ?slave? mode. on all subsequent read operations the load output register pulse is only generated by the ?master? channel (for the appropriate polarity of /a0 and /a1 (pe12024g only), as noted above) and this is fed to the ?slave? devices via the /kli-klo connection. special care must be taken when cascading devices or channels to always read in the same channel order, as well as the byte order already mentioned - see also systems application . www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 11 / 25 PE12016G/24g pin description pin name pin number i/o description pdip28 PE12016G pdip24 pe12024g /cs 1 1 input chip select. a low enables the devic e. /rd 2 2 input read. when this and /cs are active (low), the data from the output register will be present on the data bus. d0 d1 d2 d3 d4 d5 d6 d7 3 4 5 6 8 9 10 11 3 4 5 6 8 9 10 11 input/ output (3-state) lsb data bus buffer: 8-bit bidirectional buffer with 3-state outputs connected to the microprocessor system. msb /borrow 12 - output (pp) push-pull output of the counter underflow signal (PE12016G only). /carry 13 - output (pp) counter overflow signal (PE12016G only) /kli-klo 15 - input/ output (od with pull-up) cascade load input / cascade load output. open drain (od) output with internal 75k (nom) pull-up. (PE12016G only) /ready 16 - output (pp) when active low, the signal indicates to the mpu that read or write may be completed. /ready falling edge is synchronous with clk. the push pull output requires no external pull-up resistor (PE12016G only). m2 m1 m0 17 18 19 13 14 15 input input input mode select inputs (see table 1 ) ua1 ua2 20 21 16 17 input input measuring input signals www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 12 / 25 PE12016G/24g pin description - continued pin name pin number i/o description pdip28 PE12016G pdip24 pe12024g ua0 - 23 input reset input for the 24-bit counter (pe12024g only) clk 22 18 input clock. used for internal synchronisation and control timing. /a0 23 19 input byte select. a high level selects the least significant byte. /a1=1 with pe12024g a low level selects the most significant byte (/a1=high with the pe12024g) ? see table 2 . /a1 - 22 input byte select. a low level with /a0=high selects the ms-byte (bits 16-23) on the pe12024g /reset 24 20 input device reset. when active (low), the control logic is reset to a known state and the counter is cleared. /we 25 21 input write enable. when /we and /cs are active (low), the data that is on the bus is loaded into the counter. /down 26 - input cascade input for counting down. (PE12016G only) /up 27 - input cascade input for counting up. (PE12016G only) vcc 28 24 power supply voltage gnd 7, 14 7, 12 ground www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 13 / 25 PE12016G/24g operating conditions absolute maximum ratings over operating free air te mperature: symbol parameter value units v cc dc supply voltage -0.3 to + 7.0 v v in dc input voltage -0.3 to v cc + 0.3 v i in dc input current +/- 10 ma storage temperature (plastic package) -40 to +125 c dc characteristics (referred to gnd): symbol parameter test condition min typ max units v oh all except, /ready and /kli-klo output high level i oh = -20 ua v cc -0.1 v v oh d0-d7 i oh = -12 ma, v cc = 5.0v 2.4 v v oh all except d0-d7, /ready and /kli-klo i oh = -6 ma, v cc = 3.3v 2.4 v v ol output low level i oh = 20 ua 0.1 v v ih input high level ttl schmitt trigger 2.0 2.4 v v il input low level 0.5 v i cc supply current 20 mhz v cc =max 10 ma vt+ schmitt trigger positive going threshold v cc = min to max 2.4 v vt- schmitt trigger negative going threshold v cc = min to max 0.5 v v hys schmitt trigger hysteresis v cc = min to max 0.2 v i oz tristate output leakage current v cc = max or gnd -10 +10 ua input high current -10 +10 ua i ih input with pullup v in = v cc -200 -10 ua i il input low current v in = gnd -10 +10 ua recommended operating conditions: symbol parameter value units v cc dc supply voltage 4.5 to 5.5 v v cc dc supply voltage (low power application) 3.0 to 3.6 v t ac temperature range 0 to +70 c www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 14 / 25 PE12016G/24g timing requirements over recommended operating cond itions symbol parameter min typ max units tc1 clk cycle time, duty cycle 50% 50 ns tc2 pulse width low clk tr, tf<5ns 25 ns twrs pulse width, /reset input low 50 ns fmud maximum frequency, /up or /down, input duty cycle 50% (PE12016G only) 20 25 mhz twud pulse width, /up or /down input low (PE12016G only) 25 ns twk pulse width, /kli-klo input low (PE12016G only) 20 ns twrd1 pulse width, /rd input low (mode = 6 & 7) ns twrd2 pulse width, /rd input low (mode = 0 to 5) t c1 ns tdrd time between two or three* read cycles (lsb or lsb+1* and msb) 0 ns twwr pulse width, /we input low 25 ns tdwr time between two or three* write cycles (lsb or lsb+1* and msb) 0 ns tsd set up time, data prior to /we 15 ns twua0 pulse width, ua0 input high* 25 tsus set up time, /cs and /rd low before clk fallin g edge 15 ns tsa set up time, /a0, /a1* prior to /we and /cs low 10 ns tsud set up time, /up or /down rising edge before clk falling edge (PE12016G only) 20 ns tsab set up time, ua1 or ua2 prior to clk falling e dge. 15 ns tsda set up time, data prior to /we tsd ns tsbb set up time, ua2 stable before clk falling edg e 15 ns tsac set up time, ua1 or ua2 rising edge before clk fall ing edge. 15 ns tsar set up time, /a0, /a1* stable before /cs and /rd lo w after reset 10 ns tsbc set up time, ua1 or ua2 falling edge 15 ns tsr set up time, /reset high prior to clk falling e dge. 0 ns tsuc set up time, /up or /down rising edge prior to /kli-klo (input) falling edge (PE12016G only). 20 ns www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 15 / 25 PE12016G/24g timing requirements over recommended operating cond itions - continued symbol parameter min typ max units thdw hold time data after /we 10 ns twgp pulse width, ua1 input high (mode = 6) min 2 x tc1 ns twgp pulse width, ua2 input high (mode = 7) min 2 x tc1 ns tdgp pulse width, ua1 input low (mode = 6) min 2 x tc1 ns tdgf pulse width, ua2 input low (mode = 7) min 2 x tc1 ns tha address hold time after /we or /cs high 12 ns thab ua1 or ua2 hold time after clk falling edge 12 ns thda d0-d7 hold time after /a0 or /a1* change 10 ns thac ua1 high hold time after clk falling edge 12 ns thbc ua2 hold time after clk falling edge 12 ns twrh pulse width, ua0 input high 5 ns * pe12024g only www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 16 / 25 PE12016G/24g switching characteristics, (vcc=min, temperature +70 degrees) symbol parameter test conditions see appendix a (test pattern) min typ max units tdd1 access time, /rd and clk to data output valid (mode = 0 to 5) 65 ns tdd2 access time, /rd to data output valid mode = 0 to 5 2 nd byte or 3 rd byte* mode = 6 to 7 both bytes, or all three bytes (pe12024g only) 45 ns thr propagation delay /rd, /we or /cs inactive to /ready (PE12016G only) from cs 20 ns tdr propagation delay clk to /ready low (PE12016G only) 30 ns tduc propagation delay /up or /down rising edge to /carry or /borrow rising edge (PE12016G only) from /up to /carry 35 ns tdcc propagation delay from clk to /carry or /borrow rising edge (PE12016G only) from /clk to /carry or from /clk to /borrow 25 ns tdco propagation delay clk falling edge to /kli-klo falling edge (PE12016G only) 55 ns tdcb propagation delay clk rising edge to /carry or /borrow rising edge (PE12016G only) from /clk to /carry or /borrow 25 ns ted enable time /rd and /cs low to d0-d7 65 ns twco /kli-klo low output pulse width (PE12016G only) tc2 ns twcb /carry or /borrow low output pulse width (PE12016G only) twud ns twcc /carry or /borrow low output pulse width (PE12016G only) tc2 ns thdr release time, data after /rd, /cs from /cs data >01 16 zz 16 0 45 ns www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 17 / 25 PE12016G/24g fig. 8: timing ? mode 0 fig. 9: timing ? mode 1 - 5 fig. 10: timing ? mode 6-7 up or down carry or borrow ua0 t wud t wcb t wrh t duc www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 18 / 25 PE12016G/24g fig. 11: read cycle www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 19 / 25 PE12016G/24g fig. 12: write cycle www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 20 / 25 PE12016G/24g system application the implementation of a three axis control system with the PE12016G, 12024g is shown in figure 14 . the microprocessor accesses each channel, memory mapped i/o or i/o addresses with normal read or write cycles. clk frequencies up to 20mhz can be sourced directly from the microcontroller. for an external freeze, all /kli- klos can be connected together and driven by the external ?freeze-logic?. this logic must be designed such that all PE12016G/12024gs are programmed into the slave mode before the first read or write cycle appears and must be synchronised with clk. if the /read output (PE12016G only), is used, it must be externally wire-or?ed (not shown in figure 14 ) and fed to the microcontroller /ready input. an external zero pulse from the resolver can drive the pe12024g ua0 input. fig. 13: block diagram for a three-axis control sys tem 8 - bit data bus address bu s 1/2 freeze address decoder 3 system- reset reset clk wr rd d0...d7 a0...a15 7 8-bit micro- controller ua0 ua1 ua2 kli-klo clk m0 /1 /2 rd we reset cs d0...d7 a0 /1 axis 3 PE12016G/ pe12024g ua0 ua1 ua2 kli-klo clk m0 /1 /2 rd we reset cs d0...d7 a0 /1 axis 2 PE12016G/ pe12024g ua0 ua1 ua2 kli -klo clk m0 /1 /2 rd we reset cs d0...d7 a0 /1 axis 1 PE12016G/ pe12024g mode select www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 21 / 25 PE12016G/24g cascading the PE12016G figure 15 shows the cascading of two PE12016Gs for 32-bit resolution. the master (ls-word) needs to be programmed to mode 5 and the slave (ms-word) to mode 0 (count only). the /kli-klo inputs of both devices are connected together. an external pull-up is not required since it is on-chip. optional /kli-klo signal could be used as an external freeze input. in this case, both devices operate in slave mode (see figure 15 ? cascaded configuration) by generating a /freeze low pulse, synchronous with clk before the first read or write cycle appears after /reset. in normal applications, the PE12016G receiving the first read/write cycle after initialisation via a /reset, is programmed into master mode. /carry an /borrow of the master PE12016G are connected to the /up and /down inputs of the slave. if /ready is used to slow down the microprocessor read/write cycle, both /ready outputs must be or?ed to generate a common ready signal. fig. 14: cascading of two PE12016G for 32-bit resol ution ua1 ua2 vcc cs clk d0...d7 a0 we up down ua2 ua1 kli-klo m0 m1 m2 reset PE12016G master (ls-word) ready rd carry borrow cs clk d0...d7 a0 we up down ua2 ua1 kli-klo m0 m1 m2 reset PE12016G slave (ms-word) ready rd carry borrow car bor adr 8 - bit data bus a0 rd we clk d0...d7(msb) dec ready freeze reset & www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 22 / 25 PE12016G/24g pdip24/28 package dimensions package drawing: fig. 15: pdip24/28 package dimensions package availability chart and ordering code: pdip24-300 mil pdip28-600 mil PE12016G no PE12016G-pdip28 pe12024g pe12024g-pdip24 no www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 23 / 25 PE12016G/24g application notes: read cycle: the read cycle is intended and designed synchronous to the clock. special care has to be taken for the parameter t sus (the setup time of the falling edge of /rd before the falling clk edge). if t sus is not within spec, there is the possibility that the outp ut register is not updated and the same value will be read twice. therefore the microprocessor system collecting the data and PE12016G/12024g should either have the same clock or the /rd on the PE12016G/12024g ha s to be synchronized into the PE12016G/12024g clock domain via an act74 type flip flop. cascading: cascaded channels which use the /up, /down inputs f or counting have to be configured to mode 0. the /up, /down inputs will have no effect in other modes. this behaviour is different to cf32007 but not considered serious. mode 0: mode 0 (PE12016G) is only recommended for cascading . other applications have to take care of the parameter t suc . PE12016G might give out an invalid value, if this specification is not met. to avoid this, the microprocessor should take care, that dat a will only be read, when /up or /down are logically high. typically this can be achieved by g ating these inputs via microprocessor ports by discrete and/or gates. electrical design recommendations : it is recommended that the PE12016G/12024g is used without a socket and with at least 1 decoupling capcitors (100 nf) connected to vcc and gnd close t o the package. www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 24 / 25 PE12016G/24g important notice productivity engineering gmbh (pe) reserves the right t o make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any produc t or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complet e. all products are sold subject to pe?s terms and conditions of sale supplied at the time of orde r acknowledgment. pe warrants performance of its hardware products to t he specifications applicable at the time of sale in accordance with pe?s standard warranty. testing and o ther quality control techniques are used to the ext ent pe deems necessary to support this warranty. except whe re mandated by government requirements, testing of all parameters of each product is not necessarily perfo rmed. pe assumes no liability for applications assistance o r customer product design. customers are responsibl e for their products and applications using pe components. to minimize the risks associated with customer prod ucts and applications, customers should provide adequate design and operating safeguards. pe does not warrant or represent that any license, ei ther express or implied, is granted under any pe pate nt right, copyright, mask work right, or other pe intellectual property right relating to any combination, machine , or process in which pe products or services are used. informatio n published by pe regarding third?party products or services does not constitute a license from pe to use such products or services or a warranty or endorse ment thereof. use of such information may require a license from a third party under the patents or other intellectu al property of the third party, or a license from pe under the paten ts or other intellectual property of pe. resale of pe products or services with statements dif ferent from or beyond the parameters stated by pe for that product or service voids all express and any implie d warranties for the associated pe product or service and is an unfair and deceptive business practice. pe is not res ponsible or liable for any such statements. figures fig. 2: pe 12016g block diagram ................................................... ................................................... ............ 3 fig. 3: pe12024g block diagram ................................................... ................................................... ............. 3 fig. 4: direction discriminator modes ................................................... ................................................... .... 6 fig. 5: direction discriminator up clock ................................................... .................................................. 6 fig. 6: direction discriminator down clock ................................................... ............................................. 7 fig. 7: pulse width measurement ................................................... ................................................... ............ 8 fig. 8: frequency measurement ................................................... ................................................... ............... 8 fig. 9: timing ? mode 0 ................................................... ................................................... ............................. 17 fig. 10: timing ? mode 1 - 5 ................................................... ................................................... ..................... 17 fig. 11: timing ? mode 6-7 ................................................... ................................................... ....................... 17 fig. 12: read cycle ................................................... ................................................... .................................... 18 fig. 13: write cycle ................................................... ................................................... .................................... 19 fig. 14: block diagram for a three-axis control sys tem ................................................... ..................... 20 fig. 15: cascading of two PE12016G for 32-bit resol ution ................................................... ............... 21 fig. 16: pdip24/28 package dimensions ................................................... ................................................ 22 tables table 1: PE12016G/12024g operation modes ................................................... ......................................... 5 table 2: pe12024g address select ................................................... ................................................... ......... 5 table 3: ua1 and ua2 levels during reset operations ................................................... ............................ 9 www..net
PE12016G / pe12024g incremental encoder december 15, 2005 version 1.7 december 15, 2005 (version 1.7) seite 25 / 25 PE12016G/24g mailing address: productivity engineering gmbh behringstr. 7 d-71083 herrenberg germany phone: (+49) 7032 / 2798-0 fax: (+49) 7032 / 2798-29 email: info@pe-gmbh.com webpage: www.pe-gmbh.com www..net

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